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| ics for communications 4 channel adpcm controller quad adpcm peb 7274 version 1.2 pef 7274 version 1.2 data sheet 08.97 ds 1
edition 08.97 this edition was realized using the software system framemaker a . published by siemens ag, hl sw balanstra?e 73, 81541 mnchen ? siemens ag 08.97. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endan- peb 7274 revision history: current version: 08.97 previous version: preliminary data sheet 01.97 page (in previous version) page (in new version) subjects (major changes since last revision) - 5 list of figures (new) 52 52 note added (the last 15 bits ...) 72 72 input leakage current (values added for neg. temperature range, xtal1) 72 72 input/output voltage (addapted to ttl levels, test conditions added) 74 74 frame strobe delay t fsd (new) 77 77 bit clock delay t bcd = 25 ns (changed) dsync delay t dsync (new) peb 7274 pef 7274 semiconductor group 3 08.97 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.4 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.6.1 pcm-4 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.6.2 pcm-4 system using standard codec filters . . . . . . . . . . . . . . . . . . . . . .16 1.6.3 pcm-8 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.6.4 dect linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.1 adpcm coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.2 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.3 propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.4 echosuppression and speech detection . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4.1 echosuppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4.2 speech detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4.2.1 noise monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.4.2.2 speech detection preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.5 fax/modem detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.6 artificial echo loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.7 congestion tone generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.8 frame strobe outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.9 serial microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.10 boundary scan test controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.10.1 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3 register and dsp ram location description . . . . . . . . . . . . . . . . . . .46 3.1 configuration register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.2 compression rate register (crr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.3 uncompressed time slot registers (ut0 ... ut3) . . . . . . . . . . . . . . . . . .50 3.4 decoder pcm position register (dpp) . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.5 msb of pcm time slots register (msb) . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6 echo suppressor enable register (ese) . . . . . . . . . . . . . . . . . . . . . . . . .53 3.7 additional feature register (adf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.8 additional feature register 2 (adf2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.9 fax/modem detection enable register (fde) . . . . . . . . . . . . . . . . . . . . .55 3.10 fax / modem detection status register (fds) . . . . . . . . . . . . . . . . . . . . .56 3.11 dsp status register (dst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.12 command register (com) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.13 address of dsp ram register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.14 dsp ram data high byte register (datah) . . . . . . . . . . . . . . . . . . . . . .58 peb 7274 pef 7274 semiconductor group 4 08.97 3.15 dsp ram data low byte register (datal) . . . . . . . . . . . . . . . . . . . . . . 58 3.16 dsp ram loactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.16.1 programming dsp ram cells for extended features . . . . . . . . . . . . . . . 60 3.16.2 congestion tone generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.16.3 tone filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.16.4 artificial echo loss gain (ael_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.16.5 speech detector and noise monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.16.6 echo suppressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.16.7 fax/modem detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.1 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4.2 serial microcontroller interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.3 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.4 bcl timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 6.1 proposed default values for dsp locations . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 working sheet for register programming . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.1 stsi 4000 pcm-4 userboard kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.2 sipb 7274 quad adpcm kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 peb 7274 pef 7274 semiconductor group 5 08.97 figure 1: logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2: pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4: integration in pcm-4 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5: integration in pcm-4 system with automatic modem handling . . . . . . . . 15 figure 6: integration in pcm-4 systems using standard codec filters . . . . . . . . . 16 figure 7: integration in pcm-8 systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8: integration in a dect linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9: encoder block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10: decoder block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11: allocation of data to slots and within the slots . . . . . . . . . . . . . . . . . . . . 21 figure 12: decoder / encoder timing in a pcm-4 system . . . . . . . . . . . . . . . . . . . . 22 figure 13: decoder / encoder timing in a pcm-8 system . . . . . . . . . . . . . . . . . . . . 22 figure 14: echo sources in a dect pbx system . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15: echosuppressor functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16: echosuppression on the compressed side (dect system) . . . . . . . . . . 27 figure 17: echosuppresion on the uncompressed side (pcm-4/8 system). . . . . . . 27 figure 18: speech detector mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19: speech detector parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20: speech detection principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21: fax/modem tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22: frame strobe output: short frame timing, single clock mode . . . . . . . 40 figure 23: frame strobe output: short frame timing, double clock mode. . . . . . . 40 figure 24: frame strobe output: long frame timing, single clock mode. . . . . . . . 41 figure 25: frame strobe output: long frame timing, double clock mode . . . . . . . 41 figure 26: microcontroller interface timing: write access . . . . . . . . . . . . . . . . . . . . 42 figure 27: microcontroller interface timing: read access . . . . . . . . . . . . . . . . . . . . 42 figure 28: i/o waveforms for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 29: pcm interface timing in double clocking model . . . . . . . . . . . . . . . . . . . 74 figure 30: serial m c interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 31: boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 32: bit clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 33: working sheet for register programming . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 34: stsi 4000 pcm4 userboard kit (euroset not included in kit) . . . . . . . . . 81 figure 35: sipb 7274 quad adpcm kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 semiconductor group 6 08.97 peb 7274 pef 7274 overview 1 overview the four channel adpcm controller peb 7274 (quad adpcm) features four independent full duplex ada ptive differential pulse code modulation voice coders with individually selectable compression down to 16, 24, 32 or 40 kbit/s as specified by ccitt recommendation g.726. a-law, -law or 16-bit linear operation is provided. an optional echosupression algorithm is included as well as artificial echo loss insertion and a programmable tone generation. the device is optimized for operation in pcm-4 and pcm-8 systems together with the peb 2466 sicofi-4-c and the peb 2091 iec-q v5.x. an internal fax/modem recognition allows simple allocation of the data rate needed for modem transmission or connection of modems/data rate convertors as the psb 7110 isar. the quad adpcm provides two pcm interfaces allowing free selection of input and output time slots via register bit setting. a bypass mode facilitates data over voice applications. flexible applications are supported by connecting a low cost microcontroller via a serial processor interface. indirect access to dsp ram is provided via the controller interface. additional frame synchronization signals for each channel with selectable timing conditions allow the direct connection to standard codec filters. the quad adpcm is a low power consuming cmos device. it comes in a p-mqfp-44 package. 4 channel adpcm controller quad adpcm p-mqfp-44 peb 7274 pef 7274 semiconductor group 7 08.97 version 1.2 cmos type ordering code package peb 7274 q67101-h6678 p-mqfp-44 pef 7274 q67101-h6893 p-mqfp-44 1.1 features ? 4 full duplex adpcm voice coders ? 16/24/32/40 kbit/s compression rate ? ccitt g.726, g.721 compliant ? compression rate individually programmable during operation ? cascadable for pcm-8 systems ? parameterizable echosupression ? programmable tone generation ? a-law, -law or 16 bit linear operation ? pprogrammable fax/modem-tone detection, compliant to g.164 ? optional artificial echo loss compliant to etsi ets 300 175 ? stand-alone operation in pcm-4 systems without microcontroller ? a-law or -law default set per pin strapping ? 2 pcm-interfaces 1.536, 2.048 or 4.096 mhz providing 12 to 64 time slots ? frame strobe signals for standard codec filters, long frame and short frame timing ? serial microcontroller interface ? dect synchronization clock ? jtag boundary scan compliant to ieee 1149.1 ? sub-micron cmos technology ? p-mqfp-44 package peb 7274 pef 7274 overview semiconductor group 8 08.97 1.2 logic symbol figure 1 logic symbol peb 7274 pef 7274 overview semiconductor group 9 08.97 1.3 pin configuration (top view) figure 2 pin configuration (top view) peb 7274 pef 7274 overview semiconductor group 10 08.97 1.4 pin definitions and functions pin no. symbol input (i) output (o) open drain (od) function power supply pins 7, 29 v dd i supply voltage (5 v +/-5 %) 6, 28 v ss i ground (0 v) jtag boundary scan 17 tck i test clock 35 tms i test mode select, internal pullup 36 tdi i test data input, internal pullup 18 tdo o test data output pcm interface 11 dinc i data in compressed. input of adpcm data synchronous to dcl clock 10 doc o (od) data out compressed. output of adpcm data synchronous to dcl clock. open drain. 42 dinu i data in uncompressed. input of pcm data synchronous to dcl clock 9 dou o (od) data out uncompressed. output of pcm data synchronous to dcl clock. open drain. 40 fsc i frame synchronization clock. the start of time slot 0 is marked. 41 dcl i data clock. clock range 1.536 to 4.096 mhz. 23 bcl o bit clock. half the dcl clock is output on this pin. note: this pin is not included in the boundary scan path. 14 tcc o transmit control compressed, low active. tcc is low during the slots data is transmitted on doc. 15 tcu o transmit control uncompressed, low active. tcu is low during the slots data is transmitted on dou. peb 7274 pef 7274 overview semiconductor group 11 08.97 pin no. symbol input (i) output (o) open drain (od) function microcontroller interface 5cs i chip select enable to read or write data, active low. connect to v dd if not used. 8 cclk i controller data clock. shifts data from or to the device. connect to v dd if not used. 4 cdin i controller data in. cclk determines the data rate. connect to v dd if not used. 3 cdout o controller data out. cclk determines the data rate. cdout is "high z" if no data is transmitted. 2int o (od) interrupt. low active, open drain. miscellaneous function pins 24 mcl o master clock. the crystal clock is output to act as a dsp master clock for another quad adpcm. the signal is enabled by setting the bit adf2:mce. note: this pin is not included in the boundary scan path. 43 fs0 o frame sync 0. high during the time the uncompressed data of channel 0 is active on the pcm bus. 39 fs1 o frame sync 1. high during the time the uncompressed data of channel 1 is active on the pcm bus. 38 fs2 o frame sync 2. high during the time the uncompressed data of channel 2 is active on the pcm bus. 44 fs3 o frame sync 3. high during the time the uncompressed data of channel 3 is active on the pcm bus. 1 alaw i select a-law (alaw = high) or -law (alaw = low) as default setting after reset. peb 7274 pef 7274 overview semiconductor group 12 08.97 16 res i master reset, low active. 27 xtal1 i crystal in. 20.48 mhz crystal or 20.48 mhz clock signal is connected. 26 xtal2 o crystal out. 20 .48 mhz crystal is connected. leave open, if no crystal is connected. 37 dsync i/o dect sync. output or input of 800 ms or 2.4 s dect master clock. 13 pd1 i power down 1. a 1 disables dsp 1. dsp 1 holds operation of channels 0 and 1. also disables data input and output on the compressed side as well as the dect-sync generation. 12 pd2 i power down 2: a 1 disables dsp 2. dsp 2 holds operation of channels 2 and 3. disables congestion tone generator. 20, 21, 22, 30, 31, 32, 33, 34 test0.. test7 o test pins. used for production testing only. do not connect. 19 tmen i test pin. used for production testing only. active low. internal pullup. do not connect. miscellaneous function pins (contd) peb 7274 pef 7274 overview semiconductor group 13 08.97 1.5 functional block diagram figure 3 block diagram two dsp cores contain two adpcm co ders each. the i/o of the compressed data is handled by dsp 1. the tone generator resides in dsp 2. hence, if dsp 1 is disabled (pin pd1 high), no input/output of compressed data of all four channels is possible. if dsp 2 is disabled, no tone generator is provided. peb 7274 pef 7274 overview semiconductor group 14 08.97 1.6 system integration 1.6.1 pcm-4 system figure 4 gives a general overview of integration in a pcm-4 system. the register set of the quad adpcm is in a default configuration. no connection to the microcontroller is necessary. the pcm interface is working with a double data clock of 1.536 mhz coming from the iec-q v5.x. this corresponds to a number of 12 pcm time slots or 3 iom- channels respectively. the dinu and dinc pins are tied together as well as the dou and doc pins. this way, the two pcm busses are using the same physical lines. the iec-q is in the nt-te-1536 mode at the nt side and the cot-1536 mode at the lt side. it uses the pcm slots 0 and 1. there, the quad adpcm r eads and writes the compressed data. it takes the uncompressed data from the time slots 4, 5, 8 and 9 (see figure below, the most left timeslot being slot 0). the sicofi-4-c is programmed to read/write these time slots. note that the iec-q uses an iom-2 interface where control information such as c/i- commands and monitor messages are exchanged on time slots 2 and 3. these time slots should consequently not be used to exchange compressed or uncompressed data. figure 4 integration in pcm-4 system peb 7274 pef 7274 overview semiconductor group 15 08.97 the sicofi-4-c uses the 1.536 mhz pcm clock to internally generate its masterclock. the iec-q also issues a 7.68 mhz clock. this clock can be used as microcontroller clock. the iec-q v5.x allows to program this clock rate between 0.92 and 7.68 mhz. the automatic modem detection enables the peb 7274 quad adpcm to monitor the compressed and uncompressed side of the pcm highway in all four channels in parallel. this allows to dynamically allocate the data rate needed for the transmission of high speed modem signals or to hand over the control to the psb 7110 isar. the quad adpcm detects a fax/modem t one. the microcontroller then sets the compressed output of the according channel to a highly impedant state. the psb 7110 isar takes over the uncompressed receive data, performs modem operation and data rate adaptation and passes the output data onto the timeslot left open by the quad adpcm. figure 5 integration in pcm-4 system with automatic modem handling two psb 7110 isar provide 14.4 kbit/s modem transmission on all four channels. the isar occupies 3 bit leaving 5 bit for direct 14.4 kbit/s modem transmission. one isar can be used if fax operation is not expected on all four channels simultaneously. peb 7274 pef 7274 overview semiconductor group 16 08.97 1.6.2 pcm-4 system using standard codec filters the quad adpcm provides additional frame sync signals for each channel. in case the data clock is not at a rate of 1.536 mhz, it has to be generated with an additional pll. the microcontroller selects the appropriate timing conditions for the frame sync pulses. short frame and long frame mode are provided. an additional bit clock (bcl) allows to easily connect single clock mode devices (e.g. codecs) and double clock mode devices (e.g. iec-q v5.x) as well. figure 6 integration in pcm-4 systems using standard codec filters peb 7274 pef 7274 overview semiconductor group 17 08.97 1.6.3 pcm-8 system figure 7 integration in pcm-8 systems figure 7 depicts an integration in a pcm-8 system. the pcm interface is working with a double data clock of 1.536 mhz coming from the iec-q v5.x. this corresponds to a number of 12 pcm time slots or 3 iom-channels respectively. the iec-q is in the nt- te-1536 mode at the nt side and the cot-1536 mode at the lt side. it uses the pcm slots 0 and 1. there, the two quad adpcm read and write the compressed data. they take the uncompressed data from the time slots 4 to 11 (time slots count 0 to 11). the two sicofi-4-c are programmed to read/write these time slots. the dinu and dinc pins of both quad adpcm are tied together as well as the dou and doc pins. this way, the two pcm busses of the quad adpcm are using the same physical lines. this is possible by proper time slot assignment. note that the iec-q uses an iom-2 interface where control information such as c/i- commands and monitor messages are exchanged on time slots 2 and 3. these two slots should not be used for compressed or uncompressed data transfer. no additional clock generator for the pcm data clock is necessary because the 1.536 mhz pcm clock is issued by the iec-q. the iec-q also issues a 7.68 mhz clock which can be used as microcontroller clock. peb 7274 pef 7274 overview semiconductor group 18 08.97 1.6.4 dect linecard figure 8 integration in a dect linecard figure 8 presents the integration in a linecard for a pbx featuring dect basestations. the quad adpcm features flexible ac cess to arbitrary time slots of the pcm highway by its two pcm interfaces. one of the quad adpcm provides a dect synchronization clock of either 800 ms or 2.4 s period. the other quad adpcm receive this clock for synchronized reprogramming of e.g. the data rates or other registers. together with the peb 2096 octat-p or the peb 24902/peb 24911 quad iec-q as layer-1 transceivers, seamless handover is possible in the linecard. peb 7274 pef 7274 functional description semiconductor group 19 08.97 2 functional description 2.1 adpcm coder the quad adpcm contains two dsp cores each implementing the algorithms for two channels. it supports full duplex adpcm coding and encoding as specified by ccitt recommendation g.726. a-law, -law and 16 bit linear operation are selectable separately for each channel by setting the uti-register corresponding to channel i. the synchronous coding adjustment (sca) unit of the decoder (see fig. 10 ) prevents cumulative distortion occurring on tandem operation, e.g. adpcm - pcm - adpcm. it can optionally be disabled to improve the signal/noise ratio when going from pcm to analog coding. figure 9 shows the structure of the encoder as given in ccitt rec. g.726. figure 9 encoder block diagram figure 10 illustrates the structure of the decoder. peb 7274 pef 7274 functional description semiconductor group 20 08.97 figure 10 decoder block diagram 2.2 pcm interface the quad adpcm allows most flexible use of the pcm interface. it can select the time slots of the four uncompressed data streams as well as the beginning of the compressed data stream via register programming. there is a data-in line for the uncompressed data (pin dinu) and a data-in line for the compressed data (pin dinc) as well as two data- out lines for uncompressed data and compressed data respectively (pins dou and doc). if the time slots of both data streams do not overlap, both outputs and both inputs can be electrically connected. four time slots can be assigned to the four uncompressed data streams. they select the input as well as the output of the uncompressed data. the uncompressed channel assignments are controlled by the uti registers (i being the channel number 0..3). in case of single clock mode the bit msb:utmi is used to extend the programming range to a maximum of 64 time slots. the compressed data can start at any bit. the four compressed data streams are tied together. the compressed data of channel 0 comes first, then the compressed data of channel 1 etc. in the dpp register, the number n of the first compressed data bit is selected. depending on the compression rate, two, three, four or five compressed bits will be placed at the bit positions n , n+1 , n+2 etc. the first compressed bit of the second channel directly follows the last bit of the first channel. the first bit of the third channel directly foll ows the last bit of the second channel etc. if the compression rate is changed the bit positions of the higher channels change as well. in case of bitwise bypassing or a combination of compression and bypassing the same principle applies. figure 11 illustrates the relation of the frame sync signal at the fsc pin, the numbering of the bits in the frame and the beginning of the slots. double data clock mode is peb 7274 pef 7274 functional description semiconductor group 21 08.97 assumed. the user has to take care not to overlap data by multiple allocation of channels to same timeslots. figure 11 allocation of data to slots and within the slots the rising edge of the fsc marks the start of the 125 s frame. each slot consists of 8 bits. the beginning of the compressed data can be set to every bit of the frame as given in figure 11 . the compressed channel assignment is programmed via the register dpp. in case of single clock mode at 4.096 mhz only the first 256 bits may be selected as start position. care has to be taken by proper programming of the dpp and uti registers not to overlap data if the two pcm interfaces shall work on one pcm highway. input data and output data is always allocated to the same time slots. start and execution time of the dsp programs are such that coding and decoding are performed in one single frame if the slot assignment is properly chosen. that is, for the default time slot assignment as given in figure 4 as well as for the pcm-8 system shown in figure 7 , the propagation delay through two adpcm channels in a system (coding on one side, decoding on the other side) is one single frame. 2.3 propagation delay the begin of the decoder and the encoder program is tied to the frame clock at fsc. it is optimized to provide a one frame group delay for the complete encoding/decoding operation on all four channels if the time slots of uncompressed data and compressed data are assigned properly. figure 12 gives the location of the decoder start time and the encoder start time in the frame. if the uncompressed input data is read in the time slots before the encoder starts, it is available to the compressed output immediately after the encoder stops. if the compressed input data is read before the decoder starts, the uncompressed data is available to the uncompressed output immediately after the decoder stops. in the example of figure 12 , the uncompressed data is read at the time slots 4, 5, 8 and 9 before the encoder starts. it is compressed during time slot 11 and put to the doc pin in time slots 0 and 1 of the next frame. peb 7274 pef 7274 functional description semiconductor group 22 08.97 the compressed data is read at time slots 0 and 1 before the decoder starts. it is decoded during time slots 2 and 3 and put to the dou pin during time slots 4, 5, 8 and 9 in the same frame it has been read. note that the decoding takes longer than the encoding. hence, with the default time slot assignment as described in section 1.6.1 , the delay to compress data is one frame and the uncompressed data is available in the same frame. figure 12 decoder / encoder timing in a pcm-4 system if two quad adpcm devices are put together in a pcm-8 system and the dcl clock is 1.536 mhz, there are not enough time slots for the uncompressed data left before the start of the encoder. therefore, the encoder start position can be shifted to the begin of the frame by setting the adf2:ens bit to 1. if this is done in one of the two quad adpcm, the timing as given in figure 13 results. figure 13 decoder / encoder timing in a pcm-8 system peb 7274 pef 7274 functional description semiconductor group 23 08.97 the uncompressed data of slots 4 to 7 is processed during time slot 11 in the encoder of device 1 and passed to doc at slot 0 of the next frame. the uncompressed data of slots 8 to 11 is processed during slot 0 of the next frame and put to doc at slot 1. again, all channels have a one frame delay for the complete encoding/decoding operation. if the time slots are not assigned as proposed above, the delay of one or more channels may be two frames. if the dcl clock rate is higher than 1.536 mhz more than 12 time slots are available. in this case, there are several ways to assign the time slots appropriately for minimum delay. note however that the encoding time then is longer than one time slot and the decoding takes more than two time slots. the exact start and end of the decoder and the encoder at the different dcl clock rates is given in the tables below: decoder start after slot number decoder end after slot number encoder start after slot number adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 13 adf2:ens= 1 25 dcl = 1536 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 37 adf2:ens= 1 49 dcl = 2048 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 49 adf2:ens= 1 511 dcl = 4096 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 714 adf2:ens= 1 816 dcl = 1536 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 10 21 adf2:ens= 1 start of next frame start of next frame peb 7274 pef 7274 functional description semiconductor group 24 08.97 encoder end after slot number note: if adf2:ens is set to 0, 16 bit are issued at doc. if adf2:ens is set to 1, only 8 bit are issued at doc. dcl = 2048 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 13 27 adf2:ens= 1 14 29 dcl = 4096 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 25 51 adf2:ens= 1 26 53 dcl = 1536 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 start of next frame start of next frame adf2:ens= 1 0 of next frame 1 of next frame dcl = 2048 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 start of next frame 30 adf2:ens= 1 0 of next frame 0 of next frame dcl = 4096 khz adf2:dclk = 0 adf2:dclk = 1 adf2:ens= 0 28 57 adf2:ens= 1 29 59 peb 7274 pef 7274 functional description semiconductor group 25 08.97 2.4 echosuppression and speech detection the peb 7274 quad adpcm has a v ery flexible echosuppressor integrated. in addition to the direction of the echosuppressor (attenuation on the compressed or uncompressed side) all parameters required to optimize the speech detection and signal suppression are also fully programmable. all parameters are part of the dsp ram and need to be reprogrammed after every reset. no reset settings exist for dsp ram parameters. refer to the section 3.16.1 for the procedure of programming dsp ram cells. 2.4.1 echosuppression to account for echos from the far end side with up to 70 ms delay an echosuppressor is implemented in the dsp algorithms of the peb 7274. echos mainly result when converting digital speech/data information (e.g. from u interface, s 0 interface or dect interface) into analog tip/ring signals. depending on the origin of the echo the delay of the echo varies. figure 14 shows typical sources of echos in a dect pbx system connected to the public exchange with analog and digital trunk lines. figure 14 echo sources in a dect pbx system far end echos are unpredictable with respect to duration and delaytime because these parameters change with each communication connection established. unlike near end echos where these parameters can only vary within a limited bandwidth far end echos can not be cancelled. the suppression implemented instead consists of a gain stage which adds an additional attenuation to the receive path (typically 9 db) while speech is recognized in the transmit path and the receive power level does not exceed a specified limit. the receive power level limit guarantees that despite of echosuppression the participant on the other side of the line can switch echosuppression off by speaking loud. pbx central office t/r near echo pbx central office up, so up, so t/r delay 2 x 10 ms analog subscriber delay 2 x 10 ms far echo near echo peb 7274 pef 7274 functional description semiconductor group 26 08.97 the signal flow path with all programmable echosuppression parameters is illustrated in figure 15 . the programming parameters of the echosuppression are described in section 3.16.6 . figure 15 echosuppressor functionality the echosuppressor is switched off with time constant t r without any delay when the estimated receive power level is above the value programmed in es_rxpl during the time constant t pldly . as figures 16 and 17 show the peb 7274 allows also to select the direction of suppression. in dect systems typically the suppression would be performed on the compressed side (figure 16 ). this ensures that local echos which would be noticed by the speaker on side a (handy) due to the 2 x 10 ms delay are attenuated. speech detection tx time attenuation rx t f 0 es_att t r t dly if power level rx has been exceeded yes no time power level rx 0 es_rxpl t pldly db power level power estimator rx yes no suppression on/off on off peb 7274 pef 7274 functional description semiconductor group 27 08.97 figure 16 echosuppression on the compressed side (dect system) in non-dect systems like pcm-4 applications (i.e. without delay in the order of milliseconds) the far end echo from side b must be attenuated. for this reason the uncompressed peb 7274 output of side a ( = receive signal containing far end echo) will be suppressed as soon as speech is detected in the transmit path (= uncompressed input of peb 7274). this guarantees improved speech quality for side a. refer to figure 17 for details. figure 17 echosuppresion on the uncompressed side (pcm-4/8 system) basestation linecard b u i/f adpcm codec 32kbps 64kbps 32kbps 64kbps rt cot b codec adpcm u i/f 32kbps 64kbps 32kbps 64kbps peb 7274 pef 7274 functional description semiconductor group 28 08.97 echosuppressor related parameters all parameters used in conjunction with the echsuppressor are located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.6 . parameter description es_att echosuppressor attenuation determines the level of attenuation in the receive path if speech is detected in the transmit path and the estimation of receive power is below the specified limit. es_dly echosuppressor delay specifies the delay time t dly between the disappearance of speech (speechdetector: no speech) and the start of the rise time of the echosuppressor. es_rise echosuppressor rise time specifies the time t r in which the attenuation is increased from the programmed value to 0 db. es_fall echosuppressor fall time specifies the time t f in which the attenuation is decreased from 0 db to the programmed value if speech is detected in the transmit path. es_pldly echosuppressor receive power level delay this coefficient is the time constant t pldly for the power estimator of the receive signal. es_rxpl echosuppressor receive power level this parameter specifies the power level threshold for receive direction. if the signal in the receive path exceeds the programmed value the attenuation added by the echsuppressor will be switched off after t pldly has elapsed. this guarantees that despite of echosuppression the subscriber on the other end of the line can switch echosuppression off by speaking loud. peb 7274 pef 7274 functional description semiconductor group 29 08.97 2.4.2 speech detector basically the speech detector makes use of the burst characteristic of speech. that means, every fast change in signal amplitude compared to the average signal level is recognized as speech. this is done by averaging the input signal with a lowpass filter (noise monitor lowpass) and comparing the output of this lowpass with the input signal itself. as shown in figure 18 the speech detector mechanism is composed of three seperate blocks: ? power estimator in the receive path ? speech detection preprocessing in the transmit path ? noise monitor in the transmit path figure 18 speech detector mechanism the speech detection is performed by components which offer programmable parameters. these components are the logarithmic amplifier, the speech detection lowpass filter, the peak detector and the noise monitor. they have the following functions: ? logarithmic amplifier compression of the signal area of the incoming transmit signal. ? speech detection lowpass filter spike reduction of the incoming signal. sd_lp logarithmic amplifier sd_lim tx lowpass filter speech detector preprocessing peak detector sd_pds sd_pdn nm_lp nm_lplim nm_lpfade nm_lprise nm_off noise monitor offset es_rxpl es_pldly power estimate rx noise monitor on/off echosuppressor rx sd_lp pd noise monitor lowpass filter speech detector speech/ no speech peb 7274 pef 7274 functional description semiconductor group 30 08.97 ? peak detector improvement of speech detection by offering different time constants for detected and non-detected speech. ? noise monitor discriminates between speech and noise. the noise monitor comprises a lowpass filter and an programmable offset. for a detailed description refer to section 2.4.2.1 . figure 19 gives an illustration of the speech detector parameters. figure 19 speech detector parameters 2.4.2.1 noise monitor the tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. therefore the noise monitor consists of the noise monitor lowpass filter (nm_lp) and the noise monitor offset (nm_off) in two separate branches. basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). in contrast, background noise can be regarded approximately stationary from its average power. 3.14 db nm_off sd_lim - db nm_lplim adaptive range controlled by noise monitor speech no speech peb 7274 pef 7274 functional description semiconductor group 31 08.97 the noise monitor is able to discriminate between speech and noise. it consists of the noise monitor lowpass filter nm_lp and the offset nm_off. basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). background noise can be regarded approximately stationary from its averaged power. the task of the noise monitor is to recognize voice signals without any delay and to recognize background noise. since only a difference between the average signal level and the instant signal leads to speech recognition, the influence of noise on the decision is cancelled, even if the noise level exceeds the voice level. see figure 19 for illustration of the programmable parameters of the noise monitor. noise monitor lowpass filter the noise monitor lowpass filter nm_lp provides different time constants for noise (nondetected speech) and speech. it determines the average of the noise reference level. in case of background noise the level at the output of the lowpass filter is approximately the level of the input. due to the offset nm_off the comparator remains in the initial state. in case of speech the difference of the signal level between the offset branch and the lowpass branch at the comparator increases and the comparator output changes its state. at speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the lowpass branch so that the comparator output changes polarity. hence two logical levels are generated ? one for speech and ? one for noise. a small fade constant nm_lpfade enables a fast discharging of the lowpass after the end of the speech recognition. it is recommended to choose a large rising constant nm_lprise so that speech itself charges the lowpass very slowly. generally it is not recommended to program an infinite rise time nm_lprise because in that case noise approximation is disabled. the maximum value for the lowpass is limited to the programmable value nm_lplim to detect continuous tones as speech and activate the echosuppressor. offset the offset stage nm_off represents a level threshold between signal and averaged noise. by this parameter a reference level is programmed to a percentage of full speech signal. peb 7274 pef 7274 functional description semiconductor group 32 08.97 noise monitor related parameters all parameters used in conjunction with the noise monitor are located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.5 . 2.4.2.2 speech detection preprocessing as described in the preceding chapter, the noise monitor is able to discriminate between speech and noise. in very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. therefore a peak detection is required in front of the noise monitor. peak detector the peak detector bridges the very short speech pauses during a monologue so that the respective time constant has to be long. furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. but if no speech is recognized the noise monitor lowpass must be charged very fast to the averaged noise level. additionally the noise edges are to be smoothed. therefore two time constants are necessary and have to be programmed separately: sd_pds for speech and sd_pdn for noise (background) signals. hence speech mode may be detected faster and kept longer than no speech mode so that smaller breaks may not cause switching. also noise is smoothened. parameter description nm_lplim noise monitor lowpass limit this value limits the charging off the lowpass filter. a continous input signal, that has to be detected as speech, has to be above this limit. nm_lpfade noise monitor lowpass fade constant enables the fast discharge of the noise monitor lowpass after the end of speech recognition. nm_lprise noise monitor lowpass rise time determines the time the noise monitor lowpass is charged after speech is recognized. nm_off noise monitor offset specifies a level threshold between signal and noise. speech bursts mus be nm_off db above the average signal to be recognized. peb 7274 pef 7274 functional description semiconductor group 33 08.97 speech detection lowpass filter the peak detector is very sensitive to spikes. the lowpass sd_lp filters the receive signal containing noise in a way that main spikes are eliminated. due to the programmable time constant sd_lp it is possible to defuse high-energy sibilants and noise edges. logarithmic amplifier to compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. the limitation of the logarithmic amplifier can be programmed via the parameter sd_lim. sd_lim is related to the maximum pcm level. a signal exceeding the limitation defined by sd_lim is getting amplified logarithmically, while very smooth system noise below is neglected. it should be the level of the minimum system noise which is always existing. principle of speech detection the diagrams in figure 20 graphically describe the inputs and outputs of the speech detector blocks. the result is not completely identical to the implementation in the quad adpcm echosupressor but helps to understand the function of the speech detector. figure 20 speech detection principle input signal peak detector speech no speech (noise) lp2 peb 7274 pef 7274 functional description semiconductor group 34 08.97 the first diagram shows the analog representation of the input signal, since this signal form is more convenient for the readers understanding of the signal processing. in the adpcm circuits the signal is delivered to the speech detector digitally. the peak detector output is the envelope of the input signal, where short pauses are bridged. the next diagram explains the function of the noise monitor with the two branches (noise monitor offset input and noise monitor lowpass filter). in the lower diagram the result of the signal processing in the speech detector is shown. speech detector related parameters all parameters used in conjunction with the speech detection are located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.5 . parameter description sd_lim speech detection limit input signals below the level determined by sd_lim are not processed by the speech detector. usually sd_lim is programmed for a threshold that is a few db above the noise floor of the system. sd_lp speech detection lowpass this time constant determines how the main spikes are being eliminated. note that if sd_lp is large the response time of the speechdetector is long. sd_pds speech detection peak detector speech this coefficient specifies the time constant for speech signals. a large value should be programmed to avoid quick charging during speech. sp_pdn speech detection peak detector noise this coefficient specifies the time constant for noise signals. small time constants allow quick adaptation to changes of the noise level. peb 7274 pef 7274 functional description semiconductor group 35 08.97 2.5 fax/modem detection a fax/modem tone detection is implemented in each channel of the quad adpcm. typically a 2.1 khz tone is used to indicate the remote side that a fax or modem is requesting a connection. to guarantee a reliable detection of this tone fully programmable parameters are provided. these parameters allow an adjustment to individual requirements. as soon as a tone which fullfills all p rogrammed conditions is detected, an interrupt will be generated (provided the interrupt generation was enabled with the fde register). in the register fds the source of the interrupt can be read. the quad adpcm indicates the successfull detection seperately for compressed and uncompressed side with a 1. reading the fds register will automatically reset the interrupt line (int = high). every transition of bits in the fds register generates an interrupt. a 1 to 0 transition will however occure only after the device detected that no information is sent any more (power monitoring). the stopping of the 2.1 khz tone will not c ause a 1 to 0 transition. optionally each channel bit in the fds register may individually be reset to 0. this reset is performed by programming the corresponding fde:emi bit to 0 (resets the two fds detection bits of channel i for of uncompressed and compressed side to 0). after reprogramming the fde:emi bit to 1 the next interrupt will be generated as soon as the fax/modem tone criterias are fullfilled again. note: no default dsp ram values are available after a reset. all parameters need to be programmed after reset. the operation of the fax/modem detection is illustrated in figure 21 . for reliable tone detection a combination of frequency criteria and time criteria must be met. peb 7274 pef 7274 functional description semiconductor group 36 08.97 . figure 21 fax/modem tone detection the upper branches of the rx- and tx-path contain the bandpass filter and can detect modem tones. the lower branches contain the notch filter to filter out the modem signal so that the output signals of these branches represent the power in the remaining band. for speech signals the output signal of the lower branch will be large compared to the output of the upper path and vice versa for modem signals. the center frequency and bandwidth of the modem filters can be programmed using parameters md_freq and md_bw (bandpass and notch filter). the filter outputs are averaged using a lowpass filter with parameter md_lp so that the power estimate of the signals are obtained. a minimum modem level of -40 db which has to be detected is specified by ccitt standard g.164. a respective limit value can be programmed using parameter md_lim. the difference value md_diff is implemented for modem signal detection in the transmit path. if the difference of the signal energy in the modem frequency band and out of the modem frequency band is larger than md_diff a modem signal can be detected. tx md_freq bandpass filter level detection md_lev (modem detected) md_bw notch filter level detection md_lp timer md_thold t rx bandpass filter level detection notch filter level detection power estimate timer t 31 md_freq md_freq md_freq power estimate power estimate power estimate md_bw md_bw md_bw md_lp md_lp md_lp md_diff md_lev md_diff md_thold md_lim md_lim md_lim md_lim level detection level detection level detection level detection peb 7274 pef 7274 functional description semiconductor group 37 08.97 for large values of md_diff erraneous fax/modem detection for speech input signals is avoided. on the other hand modem signals with small frequency deviations or additional noise are not detected anymore. smaller values of md_diff allow fax/modem detection in a noisy environment. protection against erraneous fax/modem detection for speech input signals is however reduced. the timer (md_thold)has been implemented to eliminate the influence of transients. adjustment should be such that modem tones of minimum duration 500 ms duration can be detected as required by ccitt specification g.164. fax/modem detection related parameters all parameters used in conjunction with the fax/modem detection are located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.7 . parameter description md_freq f ax/modem detection center frequency should be adjusted to the frequency of the modem signal to be detected (2.1 khz tones). md_bw fax/modem detection bandwidth determines the bandwidth of the modem filter. md_lp fax/modem detection lowpass specifies the time constant for the power estimator. md_tbreak fax/modem detection break time tone breaks of less than the specified time are ignored. md_thold fax/modem detection hold time specifies the time the detection conditions have to be valid for fax/modem detection. md_diff fax/modem detection difference this parameter specifies the difference the outputs of the bandpass and the notch filter have to exceed. if the difference of the signal energy in the modem frequency band and out of the modem frequency band is larger than md_diff a modem signal can be detected. md_lev fax/modem detection level determines the threshold below which noise or signals are ignored. md_lim fax/modem detection limit the level programmed in md_lim is compared with the output of the modem filter. if the level of the modem signal is above md_lim modem detection can be activated. peb 7274 pef 7274 functional description semiconductor group 38 08.97 2.6 artificial echo loss an artificial echo loss (ael) can be added to the receive path. the ael gain can be programmed from -45 db to 0 db. the direction of the ael is opposite to the direction of the echo suppression as set in the ese register. the ael can be enabled for each channel independently by setting the adf register bits ea3 ... ea0 to 1. artificial echo loss related parameters the parameter used in conjunction with the ael is located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.4 md_leve the parameter specifies the level for the end of the fax/modem detection. md_time the parameter specifies the timing conditions for the end of the fax/modem detection. parameter description ael_gain artificial echo loss gain determines the level of the ael added to the receive path. peb 7274 pef 7274 functional description semiconductor group 39 08.97 2.7 congestion tone generator a programmable tone with an amplitude between -45 dbm and 0 dbm and a frequency between 0 hz and 1 khz can be put to the uncompressed data output instead of the pcm data. the adpcm data is not evaluated if the congestion tone generator is enabled. the tone can be used to create a line occupied signal already in the terminal side of a wireless local loop system in the case the air interface is occupied. the tone can be enabled for each channel independently by setting the adf register bits ec3 ... ec0 to 1. its modulation is done by enabling and disabling it at the appropriate rate. dsp 2 has to be enabled for the tone generation. congestion tone generator related parameters all parameters used in conjunction with the congestion tone generator are located in the dsp ram. a summery is given in the table below. for a detailed description please refer to section 3.16.2 . 2.8 frame strobe outputs the application in pair gain systems together with standard codec filters is supported with one frame strobe output per channel at the pins fsi (i = 0 to 3 being the channel number). there are two different timings available, referred to as short frame and long frame, respectively. the selection is done with the fst bit in the configuration register cr. cr:fst set to 1 selects short frame timing. cr:fst set to 0 selects long frame timing. if cr:fsen is set to 0, all four fsi outputs are tied to v ss . figures 22 and 23 give the timings for short framing. figure 24 and 25 illustrate the long frame timings. parameter description ct_freq congestion tone frequency ct_lev determines the level of the congestion tone ct_gain specifies the frequency gain peb 7274 pef 7274 functional description semiconductor group 40 08.97 in short frame timings the first bit starts with the falling edge of fsi. the frame strobe signal is high during one dcl period in single clock mode (adf2:dclk = 1) as well as in double clock mode (adf2:dclk = 0). figure 22 frame strobe output: short frame timing, single clock mode figure 23 frame strobe output: short frame timing, double clock mode in double clock mode, the bcl signal can be used by the recieving device to determine when the pcm data is shifted in. shofr_si bit 1 bit 2 bit 8 dout dcl fsi shofr_db bit 1 bit 2 bit 8 dout bcl dcl fsi peb 7274 pef 7274 functional description semiconductor group 41 08.97 at long frame timing the time slots are nominally coincident with the rising edge of fsi. the frame strobe signal is high during all 8 (single clock mode), 16 (double clock mode) respectively, dcl periods marking one complete time slot. figure 24 frame strobe output: long frame timing, single clock mode figure 25 frame strobe output: long frame timing, double clock mode in double clock mode, the bcl signal can be used by the recieving device to determine when the pcm data is shifted in. lonfr_si bit 1 bit 2 bit 8 dout fsi dcl peb 7274 pef 7274 functional description semiconductor group 42 08.97 2.9 serial microcontroller interface the serial microcontroller interface consists of four lines: cs , cclk, cdin and cdout. cs is used to start a serial access to the registers. following a falling edge of cs , the first eight bits received on cdin specify the command. the following data byte is stored in the selected register with the rising edge on cs . the first received bit specifies a read (bit = 0) command or a write command (bit = 1). the following five bits give the register address (msb first). figure 26 microcontroller interface timing: write access figure 27 microcontroller interface timing: read access in a read access an id-byte (co h ) is issued before the data byte as shown in figure 27 . the maximum data clock frequency to be applied at pin cclk is 7.68 mhz. cclk may pause between control and read/write byte(s). these breaks may be arbitrarly long or missing at all. cs cclk cdin cdout hi g h "z" cont rol 1 a3a2a1a0 x x a4 data b y te 76543210 cs cclk cdin cdout h i g h"z" c ontrol 0 a3a2a1a0 x x a4 identification c o h 76543210 dat a b y te 76543210 peb 7274 pef 7274 functional description semiconductor group 43 08.97 data bits at cdin are latched by the device with the rising edge of cclk. the bits at cdout are put to the line with the falling edge of cclk, they may therfore be latched by the m c with the rising edge. indirect access to the dsp ram is provided via the com register, the dst register, the data registers and the adr register. the data registers are used to either read data from or write data to the dsp ram. the read access of the other registers is only used to control the register contents. data put into the registers at an arbitrary time is valid with the next rising edge of the frame clock at fsc. if the dsync pin is input, data is valid at the next rising edge of the frame at fsc after the next falling edge of the clock at dsync. 2.10 boundary scan test controller the quad adpcm provides a boundary scan support for a cost effective board testing. it consists of: Ccomplete boundary scan for 22 signals (pins) according to ieee std. 1149.1 specification Ctest access port controller (tap) Cfour dedicated pins (tck, tms, tdi, tdo) Cone 32-bit idcode register all pins except the power supply pins, the not connected pin and pins bcl, mcl, tdi, tdo, tck, tms, xtal1 and xtal2 are included in the boundary scan. when the tap controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins tdi/tdo using clock at pin tck. the clock rate at pin tck may be up to 10 mhz. depending on the pin functionality one, two or three boundary scan cells are provided. note: there are several pins, which for chip test are used as i/o pins. please refer to section 1.4 whether these pins are inputs or outputs. however, they are included to the boundary scan as i/o pins with three scan cells. pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable peb 7274 pef 7274 functional description semiconductor group 44 08.97 the pins are included in the following sequence in the boundary scan: boundary scan number tdi CC> pin number pin name type number of scan cells 1 37 dsync i/o 3 238fs2o2 339fs1o2 440fsci 1 541dcli 1 642dinui 1 743fs0o2 844fs3o2 9 1 alaw i 1 10 2 int o2 11 3 cdout o 2 12 4 cdin i 1 13 5 cs i1 14 8 cclk i 1 15 9 dou o 2 16 10 doc o 2 17 11 dinc i 1 18 12 pd2 i 1 19 13 pd1 i 1 20 14 tcc o2 21 15 tcu o2 22 16 res i1 peb 7274 pef 7274 functional description semiconductor group 45 08.97 2.10.1 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee std. 1149.1. transitions on the pin tms cause the tap controller to perform a state change. following the standard definition 7 instructions are executable. tap controller instructions: extest is used to examine the board interconnections. when the tap controller is in the state "update dr", all output pins are updated with the falling e dge of tck. when it has entered state "capture dr" the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state "update dr", all inputs are updated internally with the falling edge of tck. when it has entered state "capture dr" the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 001 (intest) is the default value of the instruction register. sample/preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. highzq sets all pins included to the boundary scan path into a high impedance state. in this state, an in-circuit test system may drive signals onto these pins. code instruction function 000 extest external testing 001 intest internal testing 010 sample/preload snap-shot testing 011 idcode reading id code 100 clamp reading outputs 101 highzq z-state of all boundary scan output pins 11x bypass bypass operation peb 7274 pef 7274 register and dsp ram location description semiconductor group 46 08.97 clamp allows the state of the signals included in the boundary scan driven from the quad adpcm to be determined from the bound ary scan register while the bypass register is selected as the serial path between tdi and tdo. these signals will not change while clamp is selected. idcode serially reads out the 32-bit identification register via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". note: in the state test logic reset the code 011 is loaded into the instruction code register. 3 register and dsp ram location description operational modes are set per register programming. the default state of all registers after reset is such that operation in a pcm-4 system is possible without access of the microcontroller to the quad adpcm. a-law or -law oper ation can then be set by pin strapping. all registers except the fds and the dst register are of read / write type. these can be used to control the register contents and to read dsp ram data of the datal and datah registers. the address map and a register summary are given in the following table. registers with addresses 12 h to 1f h are not accessible to the user. they are used for test purposes only. note: defaults of registers with two default values given depend on the setting of the alaw pin. alaw pin low: left reset value is valid. alaw pin high: right rest value is valid. version device code manufacturer code output 0001 0000 0000 0011 0011 0000 1000 001 1 --> tdo peb 7274 pef 7274 register and dsp ram location description semiconductor group 47 08.97 table 1 register summary 1) a change in this register becomes effective only after 2 frames 2) a change in this register becomes effective in the next frame 3) no write access by the user addres s (hex) register name reset value (hex) description refer to page 00 ut0 26 or 27 uncompressed timeslot of channel 0 1) 50 01 ut1 2e or 2f uncompressed timeslot of channel 1 1) 50 02 ut2 46 or 47 uncompressed timeslot of channel 2 1) 50 03 ut3 4e or 4f uncompressed timeslot of channel 3 1) 50 04 msb 00 msb of pcm time slots 1) 53 05 crr 00 compression rate register 1) 49 06 dpp 00 decoding pcm position 1) 52 07 adf 00 additional features register 54 08 adf2 00 additional features register 2 2) 54 09 cr 00 configuration register 2) 48 0a ese 00 echosuppressor enable 53 0b fde ff fax detection enable register 55 0c fds 00 fax detection status register 3) 56 0d dst 00 dsp status register 3) 56 0e com 00 command register 57 0f adr 00 address of dsp ram block 58 10 datah 00 dsp ram data register, high byte 58 11 datal 00 dsp ram data register, low byte 58 peb 7274 pef 7274 register and dsp ram location description semiconductor group 48 08.97 3.1 configuration register (cr) the configuration register cr selects the general setting valid for all four channels. fsen frame strobe enable 1 ... enable frame strobes at pins fs3..fs0 0 ... set pins fs3 to fs0 to v ss fst frame synchronization type 0 ... selects long frame 1 ... selects short frame mclk1, mclk0 master clock selection the frequency at dcl must be disclosed to the device for proper operation as given in the table below: osb oscillator bypass 1 ... bypasses the internal oscillator if no crystal is connected to xtal1 and xtal2 0 ... when a crystal is connected to xtal1 and xtal2 ds1, ds0 dect sync mode the quad adpcm provides a dect synchronization clock of either 800 ms period or 2.4 s period at the dsync pin. the clock can also be fed into the quad adpcm if the dsync pin is programmed as input. the settings are programmed as given in the table below: fsen fst mclk1 mclk0 osb ds1 ds0 res mclk1 mclk0 clock at dcl pin 0 0 1536 khz 0 1 2048 khz 1 0 4096 khz 1 1 reserved ds1 ds0 clock period at dsync pin 0 0 dsync pin tied to v ss 0 1 input 1 0 800 ms 1 1 2.4 s peb 7274 pef 7274 register and dsp ram location description semiconductor group 49 08.97 if dsync is output, it generates a signal with a low time of 62.5 s. the falling edge of this signal is at the rising edge of fsc. if dsync is input, the contents of the registers with the addresses 0 to 6 h , 8 h and 9 h are stored with the first rising edge at the fsc pin after the falling edge at the dsync pin. this allows synchronous adaption of the compression rate and disabling/ enabling of outputs on all devices in a system. if dsync is input, adf2:sbe is dont care. the signal starts at the frame n+3 if enabled during frame n. res reset 1 ... resets the device to its default state. the effect is the same as applying a low to the res pin for 2 dsp clock cycles. the reset bit is set to low after 2 dsp cycles. 3.2 compression rate register (crr) the compression rate register crr selects the compression rate for each channel separately. cr31, cr30 compression rate for channel 3 cr21, cr20 compression rate for channel 2 cr11, cr10 compression rate for channel 1 cr01, cr00 compression rate for channel 0 the compression rates for each channel are set according to the table below: cr31 cr30 cr21 cr20 cr11 cr10 cr01 cr00 cri1 cri0 compression rate of channel i 0 0 32 kb/s 0 1 40 kb/s 1 0 16 kb/s 1 1 24 kb/s peb 7274 pef 7274 register and dsp ram location description semiconductor group 50 08.97 if the uti:m1 bit is set to one (bypass-mode, see section 3.3 ), the number of bypassed most significant bits is set by the crr register as given in the table below. the msbs of the un-compressed data are passed to the compressed location. cri1 and cri0 set to 1 internally encodes and decodes the data. hence, all features like echosuppression, ael etc. are available. note:due to the conversion law given by the -law, only at a-law operation an exact bypass operation is possible. 3.3 uncompressed time slot registers (ut0 ... ut3) the uncompressed time slot registers uti select the operation mode of channel i (i = 0, 1, 2, 3) together with the pcm time slot where the uncompressed data is taken from pin dinu and put to pin dou, respectively. ts4 ... ts0 time slot select the time slot on the pcm interface is selected where the uncompressed data is taken from and written to, respectively. as the maximum data rate is 4.096 mhz, there are in single clock mode a maximum of 64 time slots. the slots are set as given in the table below. the setting of the uti registers must take into account the available number of time slots. the msb is a part of the msb register: msb:utmi for channel i. cri1 cri0 number of bypassed bits, channel i, uti:m0 = 0 number of bypassed bits, channel i, uti:m0 = 1 00 1 4 01 2 5 10 3 6 1 1 8 -law 8 a-law ts4 ts3 ts2 ts1 ts0 m2 m1 m0 peb 7274 pef 7274 register and dsp ram location description semiconductor group 51 08.97 . m2 ... m0 compression mode selection a-law, -law, 16 bit linear operation or complete disable of the corresponding channel is selected as given below. in the 16 bit linear case the uncompressed data occupies two time slots. data is taken from and written to the slot as defined by ts4 to ts0 and the next one. the synchronous coding adjustment (sca, see figure 10 ) can be disabled. 1) these modes set the adpcm algorithm in powerdown and reset as specified by ccitt rec. g.726 2) bypass of 8 bits causes encoding and decoding providing all features as ael, echosuppression etc. real bypass only with less than 8 bit. msb: utmi ts4 ts3 ts2 ts1 ts0 slot number 0 000000 0 000011 ... 1 1111062 1 1111163 m2 m1 m0 description mode 0 0 0 channel disabled 1) powerdown 0 0 1 encoder 16-bit lin. to adpcm decoder adpcm to 16-bit lin. sca disabled linear 0 1 0 bypass 1, 2, 3 or 8 bit as set by crr register 1) bypass, data- over-voice 0 1 1 bypass 4, 5, 6 or 8 bit as set by crr register 1) 2) bypass, data- over-voice 1 0 0 encoder -law to adpcm decoder adpcm to -law sca disabled pcm without sca 1 0 1 encoder a-law to adpcm decoder adpcm to a-law; sca disabled pcm without sca 1 1 0 encoder -law to adpcm decoder adpcm to -law sca enabled pcm 1 1 1 encoder a-law to adpcm decoder adpcm to a-law; sca enabled pcm peb 7274 pef 7274 register and dsp ram location description semiconductor group 52 08.97 the default after reset is as given in the table below. the default time slots are fixed while the default compression law depends on the state at the alaw pin. 3.4 decoder pcm position register (dpp) the decoder pcm-position register dpp selects the bit in the frame where the compressed data is taken from pin dinc and put to pin doc, respectively. in double clock mode, each frame consists of not more than 256 bits, depending on the dcl clock rate. the binary content of the dpp register gives the bit number in the frame, where the compressed data begins. in bit clock mode there are up to 512 bits in each frame. in that case, the assignment of the compressed data is restricted to the first 256 bits in the frame. the compressed data is tied together. the dpp register give the location of the msb of the compressed data of channel 0. the msb of the compressed data of channel 1 directly follows the lsb of channel 0. the msb of channel 2 follows the lsb of channel 1 etc. note: if a lower frequency than 4.096 mhz is applied at the dcl pin, the setting of the dpp register must take into account the available number of bits. note: the last 15 bits of a frame must not be used as start position for the compressed data. register alaw-pin default after reset ut0 0 26 ut0 1 27 ut1 0 2e ut1 1 2f ut2 0 46 ut2 1 47 ut3 0 4e ut3 1 4f msb lsb peb 7274 pef 7274 register and dsp ram location description semiconductor group 53 08.97 3.5 msb of pcm time slots register (msb) the msb register contains the most significant bits of the time slots assignment for uncompressed data . this register is only necessary when the single bit clock mode is enabled (adf2:dclk = 1). in this case, there are 64 time slots available. if adf2:dclk is set to 0, there are only 32 time slots available and the msb:utmi bits are not taken into account. it also contains the disable bits doi of the compressed and uncompressed output. as long as the doi bit is 1, the corresponding output time slot on pins dou and doc is in z-state allowing the psb 7110 isar to pass data onto this time slot. utm3 ... 0 uncompressed time slot most significant bit (msb) of corresponding channel 3, 2, 1 or 0 do3 ... 0 0 ... enable output of corresponding channel 3, 2, 1 or 0 1 ... disable output of corresponding channel 3, 2, 1 or 0 resets adpcm algorithm 3.6 echo suppressor enable register (ese) the ese register contains the enable bits of the four echo suppressor algorithms and the direction of the suppressed echo. the other echo suppressor parameters reside in the dsp ram. they are indirectly programmed via the com, adr and data registers. e3 ... 0 0 ... disable echosuppressor of corresponding channel 3, 2, 1 or 0 1 ... enable echosuppressor of corresponding channel 3, 2, 1 or 0 d3 ... 0 direction of suppressed echo of corresponding channel 3, 2, 1 or0 0 ... the echo from transmit path to receive path of the un compressed side is suppressed 1 ... the echo from transmit path to receive path of the compressed side is suppressed. note:the direction of the ael is the opposite direction of the echosuppression. utm3 utm2 utm1 utm0 do3 do2 do1 do0 e3 e2 e1 e0 d3 d2 d1 d0 peb 7274 pef 7274 register and dsp ram location description semiconductor group 54 08.97 3.7 additional feature register (adf) the additional features register contains the enable bits of the ael and the congestion tone generator. ea3 ... 0 0 ... disables artificial echo loss ael of corresponding channel 3, 2, 1 or 0 1 ... enable artificial echo loss ael of corresponding channel 3, 2, 1 or 0 ec3 ... 0 0 ... disable congestion tone of corresponding channel 3, 2, 1 or 0 1 ... enable congestion tone of corresponding channel 3, 2, 1 or 0 3.8 additional feature register 2 (adf2) the additional features register 2 contains the bit to select double or single clock mode for the dcl clock and the bit to select the start time of the encoder algorithm. note: the ens bit should not be changed during operation to avoid cracking. dclk data clock mode the clock rate at dcl is either equal to the data rate (single clock) or twice the data rate (double clock). 0 ... selects double clock at dcl 1 ... selects single clock at dcl ens encoder start the time when the encoder algorithm starts is set according to the tables in section 2.3 . note:if adf2:ens is set to 0, 16 bit are issued at doc. if adf2:ens is set to 1, only 8 bit are issued at doc. ea3 ea2 ea1 ea0 ec3 ec2 ec1 ec0 dclk ens sbe mce peb 7274 pef 7274 register and dsp ram location description semiconductor group 55 08.97 sbe synchronous buffer enable 1 ... if dsync is output (cr:ds1 = 1), the contents of the registers with the addresses 0 to 6 h , 8 h and 9 h are stored with the first rising edge at the fsc pin after the falling edge at the dsync pin. 0 ... if dsync is ou tput (cr:ds1 =1), the contents of the registers with the addresses 0 to 6 h , 8 h and 9 h are stored with the next rising edge at the fsc pin. if dsync is input, sbe is dont care. the contents of the registers with the addresses 0 to 6 h , 8 h and 9 h are stored with the first rising edge at the fsc pin after the falling edge at the dsync pin. mce master clock enable 1 ... enables the output of the 20.48 mhz crystal clock on the pin mcl. this clock can be used for clocking other quad adpcms. 0 ... disable master clock output on pin mcl. 3.9 fax/modem detection enable register (fde) the fax/modem detection enable register contains the enable bits of the fax/modem detection. if the enable bit is set to low, the corresponding bits (compressed and uncompressed input) in the fax/modem detection status fds register will be reset. em3 ... 0 1 ... enable modem detection of corresponding channel 3, 2, 1 or 0 0 ... disable modem detection of corresponding channel 3, 2, 1 or 0 ead3 ... 0 1 ... enable automatic disable of echosuppressor of corresponding channel 3, 2, 1 or 0 as given by g.164. disables es if fax/modem is detected. 0 ... disable the automatic deactivation if the echosuppressor if a fax/modem is detected. em3 em2 em1 em0 ead3 ead2 ead1 ead0 peb 7274 pef 7274 register and dsp ram location description semiconductor group 56 08.97 3.10 fax / modem detection status register (fds) the fax/modem detection status register contains the status of the fax/modem tone detection. if a tone is detected, the corresponding bit is set to 1. the transition of any bit in the fds register causes an interrupt at the int pin. this interrupt is reset after a read of the fds register. to reset a bit of the fds register, the corresponding bit of the fde register has to be reset. if then the bit of the fde register is set to 1 again, the detection mechanism is ready for the next fax/modem detection. the end of the fax/modem transmission also resets the corresponding bit and creates a new interrupt. du3 ... 0 detection at uncompressed input of corresponding channel 3, 2, 1 or 0 dc3 ... 0 detection at compressed input of corresponding channel 3, 2, 1 or 0 3.11 dsp status register (dst) the dsp status register controls access to the datah and datal registers by the microcontroller. rdy2 1 ... dsp 2 has completed processing the current command from the microcontroller. 0 ... indicates that the command from the microcontroller to dsp 2 is not yet completely processed by dsp 2. rdy1 1 ... dsp 1 has completed processing the current command from the microcontroller. 0 ... indicates that the command from the microcontroller to dsp 1 is not yet completely processed by dsp 1. du3 du2 du1 du0 dc3 dc2 dc1 dc0 rdy2 rdy1 peb 7274 pef 7274 register and dsp ram location description semiconductor group 57 08.97 3.12 command register (com) the com register provides access to the dsp ram. the access to both dsps is simultaneously possible with the two status bits and the two command bits. the r/w bit selects read or write access. the status bits allows access to the ram. the command bit releases the content of the data register to the dsp. r/w read/write 1 ... read access to the dsp ram 0 ... write access to the dsp ram pd2 1 ... dsp 2 is deactivated 0 ... dsp 2 is activated two frames later pd1 1 ... dsp 1 is deactivated 0 ... dsp 1 is activated two frames later cmd2 a 1 indicates a read or write access of the microcontroller to dsp 2. this bit is automatically reset when dsp 2 has read the com register. cmd1 a 1' indicates a read or write access of the microcontroller to dsp 1. this bit is automatically reset when dsp 1 has read the com register. note: the pdi bit is only taken into account if the corresponding pdi pin is low. setting the pdi pin to high forces the dsp to powerdown state. note: read access to both dsp rams simultaneously is not permitted. the data would be lost as there is only one data register for high byte and low byte respectively. r/w pd2 pd1 cmd2 cmd1 peb 7274 pef 7274 register and dsp ram location description semiconductor group 58 08.97 3.13 address of dsp ram register (adr) the adr register contains the dsp ram address. the range is 0 to ff h . 3.14 dsp ram data high byte register (datah) the datah register contains the high byte of the data for/from the dsp ram. 3.15 dsp ram data low byte register (datal) the datal register contains the low byte of the data for/from the dsp ram. msb lsb msb lsb msb lsb peb 7274 pef 7274 register and dsp ram location description semiconductor group 59 08.97 3.16 dsp ram loactions access to the dsp ram is provided via the com register, the dst register, the adr register together with the datah and the datal registers. see sections 3.12 to 3.15 for register description. this section lists dsp parameters and addresses. each adress points to a 16 bit word. the 8 msb are related to the datah register, the 8 lsb are related to the datal register. the table below summarizes the location of all parameters and gives a reference to the following sections with a detailed parameter description. table 2 summary of dsp parameter locations 1) applies only to dsp 2. ram adress (hex) high byte nib. 3 nib. 2 low byte nib. 1 nib. 0 function refer to page 00 ct_freq 1) congestion tone 61 01 ct_lev 1) ct_gain 1) generator 61, 61 02 tf_bw 1) tf_res 1) tone filter 62, 62 03 tf_att 1) tf_sat 1) 63, 63 04 - ael_gain artificial echo loss 63 05 nm_lplim sd_lim speech detector 65, 64 06 sd_lp nm_off and 64, 65 07 nm_lpfade sp_pdn noise monitor 65, 64 08 nm_lprise sd_pds 65, 64 09 es_att es_dly echo suppressor 66, 66 0a es_rise es_fall 66, 67 0b es_pldly --- es_rxpl 67, 67 0c md_freq modem detection 68 0d md_bw 68 0e md_lp md_lim 68, 69 0f md_tbreak md_thold 69, 69 10 md_diff md_lev 69, 69 11 md_leve md_time 69, 70 peb 7274 pef 7274 register and dsp ram location description semiconductor group 60 08.97 3.16.1 programming dsp ram cells for extended features to make use of the peb 7274 features of echosuppression, fax/modem tone detection, tone generation and artificial echo loss special parameters located in the dsp ram must be programmed. a typical programming sequence to write parameters to a dsp ram cell and read the programmed values back for confirmation is described below. note: dsp ram cells are not loaded with default values after reset. example: load ram value for bandwidth of fax/modem detection with 100hz write dsp ram with following parameters: dsp ram adress: 0d h high byte for 100hz: 22 h low byte for 100hz: b3 h write data high register ( datah) = c0 h 22 h write data low register (datal) = c4 h b3 h write ram address for parameter ba ndwidth (adr) = bc h 0d h write simultaneously to dsp 1 and dsp 2 (com) = b8 h 03 h read if ram write operation is completed (dst) = 34 h => dst = 03 h = ok read back bandwidth ram cell for dsp 1 and dsp 2 (adr still 0d h ): read dsp1 bandwidth ram cells (com) = 38 h 81 h read if ram read operation is completed(dst) = 34 h => dst = 01 h = ok read data high register (datah) = 40 h => datah = 22 h = ok read data low register (datal) = 44 h => datal = b3 h = ok read dsp2 bandwidth ram cells (com) = 38 h 82 h read if ram read operation is completed(dst) = 34 h => dst = 02 h = ok read data high register (datah) = 40 h => datah = 22 h = ok read data low register (datal) = 44 h => datal = b3 h = ok note: dsp parameters given in tables show not the complete coding possibilities due to space limitation. if values are required that are not listed below, complete tables are available on disk. peb 7274 pef 7274 register and dsp ram location description semiconductor group 61 08.97 3.16.2 congestion tone generator congestion tone frequency (ct_freq) this parameter specifies the frequency of the congestion tone that may be output on the uncompressed side instead of the pcm data. range: 0 hz to 1 khz dsp range: 0000 h to 2000 h coding: freq [khz] = (ct_freq / 65536) x 8 congestion tone level (ct_lev) the level of the congestion tone can be programmed using this parameter. range: 0 db to -45 db, - db coding: refer to table 3 table 3 values for the congestion tone level congestion tone frequency gain (ct_gain) ct_gain determines the frequency gain. range: 0 db to -48 db, - db coding: refer to table 4 table 4 values for the congestion tone frequency gain hex value level in db hex value level in db hex value level in db hex value level in db 10 0.00 22 - 10.10 4c - 24.64 72 - 40.21 0b - 1.16 31 - 14.54 52 - 28.16 7a - 44.64 11 - 2.50 40 - 18.06 5b - 31.26 08 -10e9 13 - 5.00 42 - 22.14 67 - 36.06 hex value gain in db hex value gain in db hex value gain in db hex value gain in db 10 0.00 b2 - 7.50 91 - 18.06 8e - 42.14 21 - 3.25 a1 - 10.10 8b - 24.08 8f - 48.16 40 - 5.00 a0 - 12.04 8c - 30.10 90 - 10e9 08 - 6.02 92 - 14.54 8d - 36.12 peb 7274 pef 7274 register and dsp ram location description semiconductor group 62 08.97 3.16.3 tone filter tone filter bandwidth (tf_bw) determines the bandwidth of the tone filter. range: 0 to -1 coding: refer to table 5 table 5 values for the tone filter bandwidth tone filter resonance frequency (tf_res) range: 80 hz to 2 khz coding: refer to table 6 table 6 values for the tone filter resonance frequency hex value hex value hex value 81 0.0000000 91 - 0.5000000 b2 - 0.9062500 82 - 0.2500000 92 - 0.6250000 fa - 0.9980469 83 - 0.3750000 94 - 0.7187500 84 - 0.4375000 a2 - 0.8125000 hex value freq. in hz hex value freq. in hz hex value freq. in hz hex value freq. in hz 81 2000.00 93 1034.83 b4 480.31 dc 210.78 82 1678.28 9c 858.33 bc 423.03 f3 125.87 83 1510.57 a3 721.37 c3 357.05 fa 79.59 8f 1321.82 ac 601.07 cc 298.43 peb 7274 pef 7274 register and dsp ram location description semiconductor group 63 08.97 tone filter attenuation factor (tf_att) determines the out-of-frequency attenuation. range: 0 db to 48 db coding: refer to table 7 table 7 tone filter attenuation tone filter saturation amplification (tf_sat) range: -12 db to 12 db coding: refer to table 8 table 8 values for tone filter saturation amplification 3.16.4 artificial echo loss gain (ael_gain) determines the level of the ael added to the receive path. range: 0 db to -45 db, - db coding: refer to table 3 (ct_lev) hex value atten. in db hex value atten. in db hex value atten. in db hex value atten. in db f1 48.16 d0 30.10 b0 18.06 90 6.02 f0 42.14 c0 24.08 a0 12.04 80 0.00 e0 36.12 hex value ampl. in db hex value ampl. in db hex value ampl. in db hex value ampl. in db 00 12.041 41 4.048 7c -0.493 b9 -7.180 10 9.542 32 2.961 6b -1.025 a9 -8.519 20 7.959 72 2.006 4a -1.972 99 -12.041 30 7.044 1a 1.023 ca -3.059 08 -10e9 70 6.088 3c 0.462 49 -5.494 21 5.460 09 0.000 f9 -6.089 peb 7274 pef 7274 register and dsp ram location description semiconductor group 64 08.97 3.16.5 speech detector and noise monitor speech detection limit (sd_lim) this parameter determines the maximum limit of a signal for speech detection. range: -96 db to 0 db dsp range: 00 h to 7f h coding: limit [db] = -96.32 + sd_lim x 0.7525 speech detection lowpass (sd_lp) this parameter specifies how the main spikes of the signal are being eliminated. range: 1 ms to 170 ms coding: refer to table 9 table 9 values for the time constant peak detector noise (sd_pdn) this time constant specifies the . range: 1 ms to 170 ms coding: refer to table 9 (sd_lp) peak detector speech (sd_pds) this time constant specifies the . range: 1 ms to 170 ms coding: refer to table 9 (sd_lp) hex value time in ms hex value time in ms hex value time in ms hex value time in ms 00 0.94 34 15.00 54 60.17 64 120.41 0d 2.00 41 21.27 5b 73.08 6d 132.07 1e 4.00 44 30.06 61 85.27 6b 146.22 23 7.05 51 42.60 62 102.34 71 170.60 peb 7274 pef 7274 register and dsp ram location description semiconductor group 65 08.97 noise monitor lowpass limit (nm_lplim) this parameter determines the maximum value for the lowpass to detect continous tones as speech and to activate the echosuppressor. range: 0 db to 47 db dsp range: 00 h to 3f h coding: limit [db] = nm_lplim x 0.7525 noise monitor offset (nm_off) specifies a level threshold between signal and noise. range: 0 db to 47 db dsp range: 00 h to 3f h coding: limit [db] = nm_off x 0.7525 noise monitor lowpass fade constant (nm_lpfade) the fade constant enables the fast discharge of the noise monitor lowpass after the end of speech recognition. range: 1 ms to 170 ms coding: refer to table 9 (sd_lp) noise monitor lowpass rise time (nm_lprise) this time constant determines the time the noise monitor is charged after speech is recognized range: 4 s to 58 s coding: refer to table 10 table 10 values for the time constant of the noise monitor lowpass hex value time in ms hex value time in ms hex value time in ms hex value time in ms 00 4.10 0d 8.46 1c 17.48 2c 34.95 01 5.46 11 10.92 21 21.85 31 43.69 02 6.55 12 13.11 22 26.21 32 52.43 04 7.71 13 14.56 24 30.84 33 58.25 peb 7274 pef 7274 register and dsp ram location description semiconductor group 66 08.97 3.16.6 echo suppressor echosuppressor attenuation (es_att) the parameter es_att determines the level of attenuation att (refer to figure 15 ) in the receive path if speech has been detected in the transmit path and the estimation of receive power is below specified limit. range: 0 db to -16 db dsp range: 80 h to 14 h coding: suppressor attenuation [db] = 20 x log (es_att / 128) echosuppressor delay (es_dly) es_dly specifies the delay time t dly between the disappearance of speech in the transmit path (speechdetector = no speech) and the start of the fall time of the echosuppressor. range: 4 ms to 1020 ms dsp range: 00 h to ff h coding: t dly [ms] = 4 x es_dly echosuppressor rise time (es_rise) es_tr specifies the rate at which attenuation is increased from 0 db to the programmed value if speech was detected by the speech detector. this rate determines the rise time t r . range: 0.025 db/ms to 5.6 db/ms coding: refer to table 11 table 11 values for the rate determing the rise time hex value rate in db/ms hex value rate in db/ms hex value rate in db/ms hex value rate in db/ms 7a - 0.025 43 - 0.306 22 - 1.370 11 - 3.336 61 - 0.101 3c - 0.510 21 - 1.647 07 - 4.520 53 - 0.152 31 - 0.819 1c - 2.066 03 - 5.066 51 - 0.203 2c - 1.025 12 - 2.768 02 - 5.652 peb 7274 pef 7274 register and dsp ram location description semiconductor group 67 08.97 echosuppressor fall time (es_fall) this parameter determines the rate at which attenuation is decreased from the programmed value to 0 db if speech in the transmit path disappeared or the power level in the receive path exceeded the specified value. this rate determines the fall time t f . range: 0.01 db/ms to 2.13 db/ms coding: refer to table 12 table 12 values for the rate determing the fall time echosuppressor reveice power level delay (es_pldly) this coefficient specifies the time constant for the power estimator of the receive signal. range: 180 m s to 16 ms dsp range: 01 h to 07 h (only the 4 msbs are used) coding: t pldly [ms] = -0.125 / ln (1-2 -es_pldly ) echosuppressor reveice power level (es_rxpl) the es_rxpl parameter specifies the power level threshold for receive direction. if the signal in the receive path exceeds the programmed value the attenuation added by the echosuppressor will be switched off after t pldly has elapsed. this guarantees that despite of echosuppression the participant on the other side of the line can switch off echosuppression by speaking loud. range: - db, -48 db to 0 db dsp range: 00 h to ff h coding: threshold [db] = 20 x log (es_rxpl / 256) hex value rate in db/ms hex value rate in db/ms hex value rate in db/ms hex value rate in db/ms 72 0.010 23 0.304 12 0.675 03 1.210 5b 0.029 21 0.405 11 0.809 02 1.344 41 0.101 1c 0.507 0c 1.010 01 1.609 31 0.203 13 0.608 05 1.110 00 2.138 peb 7274 pef 7274 register and dsp ram location description semiconductor group 68 08.97 3.16.7 fax/modem detection fax/modem detection center frequency (md_freq) the parameter md_freq specifies the center frequency of the fax/modem tone that is to be detected. range: 1.5 khz to 2.5 khz coding: refer to table 13 table 13 values for the fax/modem detection center frequency fax/modem detection bandwidth (md_bw) the parameter md_bw specifies the range around the center frequency within the fax/ modem tone detection is allowed. range: 1 hz to 500 hz coding: refer to table 14 table 14 values for the fax/modem detection bandwidth fax/modem detection lowpass (md_lp) this parameter specifies the time constant for the power estimators in the fax/modem detection. range: 1 ms to 170 ms coding: refer to table 9 hex value freq. in hz hex value freq. in hz hex value freq. in hz hex value freq. in hz 01 4e 1500 1b 80 1800 a2 62 2100 82 cc 2400 02 cd 1600 22 64 1900 93 07 2200 81 4f 2500 0c 51 1700 01 80 2000 8c 4c 2300 hex value freq. in hz hex value freq. in hz hex value freq. in hz hex value freq. in hz c8 4c 1.09 32 c5 50.03 13 30 200.83 0d bc 350.04 49 ea 10.06 22 b3 100.10 0a 36 250.19 04 17 400.17 45 85 20.01 1b b6 150.02 0b 2c 300.39 02 23 500.37 peb 7274 pef 7274 register and dsp ram location description semiconductor group 69 08.97 fax/modem detection limit (md_lim) the level programmed in md_lim is compared with the output of the modem filter. if the level of the modem signal is above md_lim fax/modem detection can be activated. range: 0 db to 96 db dsp range: 7f h to 00 h coding: limit [db] = -96.32 + sd_lim x 0.7525 fax/modem detection break time (md_tbreak) tone breaks less than the specified time are ignored. range: 0.5 ms to 127.5 ms resolution: 01 h to ff h coding: time [ms] = 0.5 x md_tbreak fax/modem detection hold time (md_thold) md_thold specifies the time the detection conditions have to be valid for fax/modem detection. range: 8 ms to 2 s resolution: 01 h to ff h coding: time [ms] = 8 x md_thold fax/modem detection difference (md_diff) this parameter specifies the difference the outputs of the bandpass and the notch filter have to exceed. if the difference of the signal energy in the modem frequency band and out of the modem frequency band is larger than md_diff a modem signal can be detected. range: - 96 db to 96 db dsp range 00 h to ff h coding: delta [db] = sign (md_diff) x | md_diff | x 0.7525 | md_diff | are the 7 lsbs of the ram location. fax/modem detection level (md_lev) md_lev determines the threshold below which noise or signals are ignored. range: 0 db to 96 db resolution: 00 h to 7f h coding: level [db] = md_lev x 0.7525 peb 7274 pef 7274 register and dsp ram location description semiconductor group 70 08.97 fax/modem end of detection level (md_leve) the parameter specifies the level for the end of the fax/modem detection. range: 0 db to 96 db resolution: 00 h to 7f h coding: level [db] = md_lev x 0.7525 fax/modem end of detection time (md_time) the parameter specifies the timing conditions for the end of the fax/modem detection. range: 8 ms to 2 s resolution: 01 h to ff h coding: time [ms] = 8 x md_time peb 7274 pef 7274 electrical characteristics semiconductor group 71 08.97 4 electrical characteristics 4.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol limit values unit ambient temperature under bias: peb pef t a t a 0 to 70 - 40 to 85 c c storage temperature t stg - 65 to 125 c voltage on any pin with respect to ground v s - 0.3 to v dd + 0.3 v maximum voltage on any pin v max 7v peb 7274 pef 7274 electrical characteristics semiconductor group 72 08.97 4.2 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. peb: t a = 0 to 70 c; v dd = 5 v 5 %, v ss = 0 v pef: t a = C 40 to 85 c; v dd = 5 v 5 %, v ss = 0 v parameter symbol limit values unit test condition min. typ. max. high level input voltage v ih 2.0 v dd + 0.3 v low level input voltage v il C 0.3 0.8 v low level input leakage current i ll C 1 m a v in = v ss t a 3 0 c all pins except xtal1 C 10 m a v in = v ss C 40 c t a < 0 c all pins except xtal1 high level input leakage current i lh 1 m a v in = v dd t a 3 0 c all pins except xtal1 10 m a v in = v dd C 40 c t a < 0 c all pins except xtal1 xtal1 leakage current i lx 10 m a 0 v < v in < v dd to 0 v whole temperature range high level output voltage v oh 2.4 v i oh = - 400 m a low level output voltage v ol 0.45 v i ol = 7 ma (pins doc, dou, int ) i ol = 2 ma (all other pins) power supply current i cc 60 ma operational 10 ma both dsps in power down mode peb 7274 pef 7274 electrical characteristics semiconductor group 73 08.97 4.3 capacitances 4.4 ac characteristics ambient temperature under bias range, v dd = 5 v 5 %. inputs are driven at 2.4 v for a logical 1 and at 0.4 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and at 0.8 v for a logical 0. the ac testing input/output waveforms are shown below. figure 28 i/o waveforms for ac tests t a = 25 c; v dd = 5 v 5 %, v ss = 0 v parameter symbol limit values unit min. max. input capacitance c in 10 pf output capacitance c out pf i/o capacitance c i/o pf peb 7274 pef 7274 electrical characteristics semiconductor group 74 08.97 4.4.1 pcm interface timing figure 29 pcm interface timing in double clocking model parameter symbol limit values unit min. max. dcl clock period t dcl 244 ns dcl pulse width t wl, t wh 53 ns fsc setup time t fs 20 ns fsc hold time t fh 10 ns data out delay t dod 60 ns data in setup time t dis 73 ns data in hold time t dih 50 ns tristate control delay t tcd 50 ns frame strobe delay t fsd 50 ns t fh t fs dis t dod t dih t fsc dcl dinc doc dinu dou t dcl wh t t wl tcd t tcc tcu fsi fsd t peb 7274 pef 7274 electrical characteristics semiconductor group 75 08.97 4.4.2 serial microcontroller interface timing figure 30 serial m c interface timing ial parameter symbol limit values unit min. max. clock period t p 130 ns chip select setup time t css 0ns chip select hold time t csh 10 ns cdin setup time t cdins 20 ns cdin hold time t cdinh 20 ns cdout data out delay t cdoutd 40 ns uc_tim t csh t css t p t cdins t cdinh ~ ~ ~ ~ ~ ~ ~ ~ cs cclk cdin cdout cdoutd t ~ ~ ~ ~ peb 7274 pef 7274 electrical characteristics semiconductor group 76 08.97 4.4.3 boundary scan timing figure 31 boundary scan timing parameter symbol limit values unit min. max. test clock period t tcp 100 - ns test clock period low t tcpl 40 - ns test clock period high t tcph 40 - ns tms set-up time to tck t mss 20 - ns tms hold time from tck t msh 20 - ns tdi set-up time to tck t dis 20 - ns tdi hold time from tck t dih 20 - ns tdo valid delay from tck t dod -40ns peb 7274 pef 7274 electrical characteristics semiconductor group 77 08.97 4.4.4 bcl timing figure 32 bit clock timing ial parameter symbol limit values unit min. max. bit clock delay t bcd 25 ns dsync delay t dsync 80 ns fsc dcl bcl t bcd dsync t dsync peb 7274 pef 7274 package outlines semiconductor group 78 08.97 5 package outlines plastic package, p-mqfp-44 (plastic metric quad flat package) semiconductor group 79 08.97 peb 7274 pef 7274 appendix 6 appendix 6.1 proposed default values for dsp locations ram adress (hex) function proposed value (hex) effect 00 tone generator 0d 99 ct_freq = 425 hz 01 22 08 ct_lev = -10 db, ct_gain = -6 db 02 tone filter fa bc tf_bw = -0.99, tf_res = 423 hz 03 f1 09 tf_att = 48 db, tf_sat = 0 db 04 artificial echo loss 00 4c ael_gain = -24.64 db 05 speech detector 10 4a nm_lplim = 12 db, sd_lim = -40 db 06 1e 08 sd_lp = 4 ms, nm_off = 6 db 07 41 44 nm_lpfade = 21 ms, sd_pdn = 30 ms 08 00 62 nm_lprise = 4s, sd_pds = 102 ms 09 echo suppressor 20 10 es_att = -12 db, es_dly = 64 ms 0a 11 21 es_rise = -3.3 db/ms es_fall = 0.4 db/ms 0b 50 51 es_pldly = 4 ms, es_rxpl = -10 db 0c modem detection a2 62 md_freq = 2100 hz 0d 22 b3 md_bw = 100 hz 0e 31 00 md_lp = 10 ms, md_lim = -96 db 0f 02 32 md_tbreak = 1 ms, md_thold =0.4 s 10 10 45 md_diff = 12 db, md_lev =-44 db 11 3b 3e md_leve = -44 db, md_time = 0.5 s peb 7274 pef 7274 appendix semiconductor group 80 08.97 6.2 working sheet for register programming figure 33 working sheet for register programming peb 7274 pef 7274 appendix semiconductor group 81 08.97 6.3 development tools 6.3.1 stsi 4000 pcm-4 userboard kit the stsi 4000 kit consists of a r emote t erminal (rt) board and a c entral o ffice t erminal (cot) board to set up a fully operational pcm-4 demonstration. these boards can be combined with standard analog telephones and a standard analog pbx to have a complete system. the principle of stsi 4000 is shown in figure 34 . figure 34 stsi 4000 pcm4 userboard kit (euroset not included in kit) via a v.24 connection it is possible to read and write to all peb 7274 and peb 2091 v5.x registers. addtional commands allow to control and monitor peb 2466 specific functions like hook on/off detection, channel allocation etc. this allows to program very efficiently different configurations and test device functionality. alternatively the user can download his own c165 program to test realtime behavior. from mid 1997 onwards additionally a software package including sourcecode will be available which p rovides basic modules to operate the stsi 4000 as a pcm-4 system without the need for external v.24 interfaces. the stsi 4000 boards contains all hardware required in typical pcm-4 system with the exception of phantom power-supply & feeding and ringing / ttx generation. description part number ordering code pcm-4 userboard kit stsi 4000 q67100-h6865 slic slic slic slic 2091 2466 7274 c165 2091 2466 7274 c165 u euroset line 8 pbx rt cot v24 v24 11 12 13 15 16 17 18 14 tel. no. stsi 4000 peb 7274 pef 7274 appendix semiconductor group 82 08.97 6.3.2 sipb 7274 quad adpcm kit the sipb 7274 quad adpcm kit consists of a sipb 7274 board containing two quad adpcm controllers operating back-to-back, a evc50 microcontroller board based on a c513 processor and the evc50 bus to connect optionally (not included in sipb 7274 kit) a peb 2465/6 evaluation board (e.g. sips 2466). this configuration allows fast testing of all peb 7274 features. figure 35 sipb 7274 quad adpcm kit pcm coded (uncompressed) data is extracted/inserted at pcm a connector and compressed by peb 7274 (a). optionally the compressed in- and outputs of peb 7274 (b) can directly connected to those of peb 7274 (a) to provide a back-to back operation of device a and device b. the uncompressed data of peb 7274 (b) can be extracted/ inserted at connector pcm b. numerous access points on the board allow easy monitoring of all peb 7274 signals. description part number ordering code quad adpcm kit sipb 7274 q67100-h6866 evc50 sipb7274 sips2466 v24 aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a a a a a a a a a a a a a a a a a a a a a a aa aaaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaaa slic pcm aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a a a a a a a a a a a a a a a a a a a a a a a a aa aaaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaaa slic aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a a a a a a a aaaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaaa slic aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a a a a a a a a aaaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaaa slic peb 7274 a pcm a peb 7274 b pcm b me?punkte me?punkte doc dic dic doc dou dou diu diu evc50-bus wg- pcm4 semiconductor group 83 08.97 peb 7274 pef 7274 index b boundary scan ................................ 43 c congestion tone .............................. 39 d dect .............................................. 26 e echosuppression direction .............. 26 f fax/modem tone detection ........... 36 frame strobe .................................. 39 i id-byte ............................................ 42 isar ............................................... 15 n noise monitor .................................. 30 p peak detector .................................. 32 propagation delay ........................... 21 r receive power level ........................ 25 s sca ................................................ 19 serial m c interface .......................... 42 synchronous coding adjustment ..... 19 |
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